PLL-Taktpuffer CY2304SXI-1, 1 SOIC, 8-Pin

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RoHS Status: kompatibel (Zertifikat anzeigen)
Produktdetails

The CY2304 is a 3.3 V zero delay buffer designed to distribute high-speed clocks in PC, workstation, datacom, telecom, and other high performance applications. The part has an on-chip phase-locked loop (PLL) that locks to an input clock presented on the REF pin. The PLL feedback is required to be driven into the FBK pin, and can be obtained from one of the outputs. The input-to-output skew is guaranteed to be less than 250 ps, and output-to-output skew is guaranteed to be less than 200 ps. The CY2304 has two banks of two outputs each. The CY2304 PLL enters a power down state when there are no rising edges on the REF input. In this mode, all outputs are three-stated and the PLL is turned off, resulting in less than 25 μA of current draw. Multiple CY2304 devices can accept the same input clock and distribute it in a system. In this case, the skew between the outputs of two devices is guaranteed to be less than 500 ps. The CY2304 is available in two different configurations.

Technische Daten
Eigenschaft Wert
Anzahl der Elemente pro Chip 1
Versorgungsstrom max. 45 mA
Eingangsfrequenz max. 133MHz
Montage-Typ SMD
Gehäusegröße SOIC
Pinanzahl 8
Abmessungen 4.97 x 3.98 x 1.47mm
Länge 4.97mm
Breite 3.98mm
Höhe 1.47mm
Arbeitsspannnung max. 3.6 V
Betriebstemperatur max. +85 °C
Ausgangsfrequenz max. 133.3MHz
Arbeitsspannnung min. 3 V
Ausgangsfrequenz min. 10MHz
Betriebstemperatur min. -40 °C
Voraussichtlich ab 07.04.2020 verfügbar.
Preis pro: Stück (In einer Stange von 97)
9,103
(ohne MwSt.)
10,833
(inkl. MwSt.)
Stück
Pro Stück
Pro Stange*
97 - 194
9,103 €
882,991 €
291 - 485
8,294 €
804,518 €
582 - 970
7,763 €
753,011 €
1067 +
7,121 €
690,737 €
*Bitte VPE beachten
Nicht als Expresslieferung erhältlich.