PLL-Taktpuffer CY2308SXI-1H, 1 SOIC, 16-Pin

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RoHS Status: kompatibel (Zertifikat anzeigen)
Produktdetails

The CY2308 is a 3.3 V Zero Delay Buffer designed to distribute high speed clocks in PC, workstation, datacom, telecom, and other high performance applications. The part has an on-chip PLL that locks to an input clock presented on the REF pin. The PLL feedback is driven from external FBK pin, so user has flexibility to choose any one of the outputs as feedback input and connect it to FBK pin. The input-to-output skew is less than 250 ps and output-to-output skew is less than 200 ps. The CY2308 has two banks of four outputs each that is controlled by the select inputs as shown in the table Select Input Decoding on page 3. If all output clocks are not required, Bank B is three-stated. The input clock is directly applied to the output for chip and system testing purposes by the select inputs. The CY2308 PLL enters a power down state when there are no rising edges on the REF input. In this mode, all outputs are three-stated and the PLL is turned off resulting in less than 25 μA of current draw.

Technische Daten
Eigenschaft Wert
Anzahl der Elemente pro Chip 1
Versorgungsstrom max. 70 mA
Eingangsfrequenz max. 133.3MHz
Montage-Typ SMD
Gehäusegröße SOIC
Pinanzahl 16
Abmessungen 9.98 x 3.98 x 1.47mm
Länge 9.98mm
Breite 3.98mm
Höhe 1.47mm
Arbeitsspannnung max. 3.6 V
Betriebstemperatur max. +85 °C
Ausgangsfrequenz max. 133.3MHz
Arbeitsspannnung min. 3 V
Betriebstemperatur min. -40 °C
Ausgangsfrequenz min. 10MHz
48 lieferbar innerhalb von 2 Werktag(en) (Mo-Fr).
Preis pro: Stück (In einer Stange von 48)
5,665
(ohne MwSt.)
6,741
(inkl. MwSt.)
Stück
Pro Stück
Pro Stange*
48 - 48
5,665 €
271,92 €
96 - 96
5,409 €
259,632 €
144 - 240
5,101 €
244,848 €
288 - 480
4,712 €
226,176 €
528 +
4,108 €
197,184 €
*Bitte VPE beachten
Nicht als Expresslieferung erhältlich.